The present invention relates to a semiconductor memory device and a method for storing information in the semiconductor memory device, based on innovational operational principle.
Recently semiconductor integrated circuits have made remarkable progress, and higher speed and higher integration are increasingly needed. Semiconductor devices using MOSFETs of silicon semiconductor are especially remarkably higher integrated. For example, dynamic memories (DRAMs) of 1 MOS memory cell type that uses one MOSFET as a memory cell are presently marketed in DRAMs of capacities as large as 1M to 4M bit. DRAMs of large capacities of 64M to 128M bit are in test fabrication.
Accompanying higher integration of DRAMs, transistors and condensers constituting the memory cells are increasingly micronized. The size of the memory cells has been down-sized to 2 .mu.m square. In a DRAM of 1 MOS memory type, it is necessary to make a capacity of the condenser larger relative to external capacities, as of wires because memory states of 0 and 1 are discriminated by electric charge amounts accumulated in the condenser, and the condenser requires a large surface area. The condenser in a memory cell of a small area has the surface area increased by forming grooves in the semiconductor substrate or forming the condenser in a fin structure. But even these means have found it difficult to further micronize the condenser.
As semiconductor memory devices, in addition to DRAMs, electrically programmable ROMs (EPROMs) are known (S. M. Sze "Physics of Semiconductor Devices", p. 501, A Wiley-InterScience Publication, 1981). In an EPROM as well, one memory cell requires three lines which take time for electrical writing. Even in the case that two lines are used, very high voltages are required which is a serious obstacle to the higher integration.
In such circumstances, memory devices (static RAMs (SRAMs)) using differential negative resistance due to quantum effect, especially resonant tunnel effect is being studied (Federico Capasso (Ed.), "Physics of Quantum Electron Devices", pp. 207-208, Springer-Verlay, 1990; Y. Watanabe, et al. "Monolithic Integration of InGaAs/InAlAs Resonant Tunneling Diode and HEMT for Single-Transistor Cell SRAM Application", IEEE IEDM 92-475, 1992).
For example, a memory device which uses a resonant tunnel barrier (RTB) as a load device of a FET, an SRAM device which includes two resonant tunnel barriers serially connected to each other, and in which information is written by changing voltages at two ballast points of the resonant tunneling barriers by the gate electrode of an adjacent FET to write information, and this FET reads the stored information, an SRAM device in which a threshold diode provided below two resonant tunneling barriers reads and writes, and other devices are proposed.
But in these memory devices as well, 3 or more lines are provided per one memory cell, and accordingly an area of the memory cell cannot be much decreased. This is a problem.
These memory devices retain stored information by valley currents of the resonant tunnel barriers (RTBs), and to this end it is preferred that a valley current is sufficiently small with respect to a peak current. But presently a ratio of the peak current and the valley current is about 10-100. A problem is that the valley current cannot be made sufficiently small.